The present disclosure relates generally to pipelined microprocessors. More particularly, the present disclosure relates to dynamic selection of pipeline depth for such microprocessors.
In order to improve instruction throughput, microprocessors are often pipelined. Pipelining creates stages with state elements that are clocked at a higher frequency than could be achieved without pipelining. The clock power consumed by these state elements is typically the largest active power component of a microprocessor.
In some handheld microprocessor applications, the voltage of the microprocessor is dynamically controlled by a voltage controller to use the lowest possible level of power for a particular application. However, the voltage controller generally cannot reduce the voltage below the process Vmin without risking failure of the microprocessor to perform. Consequently, the power consumed exceeds what otherwise would be necessary for the application. This power is wasted and may directly impact battery life or other power parameters.